+++ /dev/null
-4-io-pin-blinky
+++ /dev/null
-dea43fb213fffca688938b96a265a788797ef3f4 11
-41ecca7377d50d23f66177ded872cd5c03503035 2-simple-blinky-100MHz
-dea43fb213fffca688938b96a265a788797ef3f4 4-io-pin-blinky
-4500b8db379f48245b0e560355cdce3a4c1d132f 1-simple-blinky
-29d00ba31af5afb6159f71a22930cb8b4d884965 3-systick-blinky
+++ /dev/null
-[paths]
-default = http://bitbucket.org/jpc/lpc1768
+++ /dev/null
-revlogv1
-store
-fncache
+++ /dev/null
-data/.hgignore.i
-data/.hgtags.i
-data/CMSIS/LPC17xx.h.i
-data/CMSIS/core_cm3.h.i
-data/CMSIS/system_LPC17xx.c.i
-data/CMSIS/system_LPC17xx.h.i
-data/LPC1768-flash.ld.i
-data/Makefile.i
-data/io-pin.h.i
-data/io-pin.ss.i
-data/main.c.i
-data/quiet.i
-data/startup.c.i
+++ /dev/null
-11 dea43fb213fffca688938b96a265a788797ef3f4 00b4faae4502de06a90031206454daa0ded1369f
-7 41ecca7377d50d23f66177ded872cd5c03503035
-
-0000000000000000000000000000000000000000 2-simple-blinky-100MHz
-0000000000000000000000000000000000000000 1-simple-blinky
-0000000000000000000000000000000000000000 3-systick-blinky
+++ /dev/null
-default
\ No newline at end of file
+++ /dev/null
-0
-pull
-http://bitbucket.org/jpc/lpc1768
+++ /dev/null
-syntax: glob
-*.d
-*.o
-*.elf
-*.hex
-*.bin
-*.dump
-*.map
+++ /dev/null
-bb46c18616910e1ce3f962a2831a888865057518 1-simple-blinky
-765e4649efad723b7bf4d47773d9b784e5d8f9c3 2-simple-blinky-100MHz
-0a00a016c609c4a31f9c2b1fc7dc4ea5958ba8c3 3-systick-blinky
-0a00a016c609c4a31f9c2b1fc7dc4ea5958ba8c3 3-systick-blinky
-390e9530c93f57868311aa2ab69c67c4cce2226a 3-systick-blinky
-bb46c18616910e1ce3f962a2831a888865057518 1-simple-blinky
-0000000000000000000000000000000000000000 1-simple-blinky
-765e4649efad723b7bf4d47773d9b784e5d8f9c3 2-simple-blinky-100MHz
-0000000000000000000000000000000000000000 2-simple-blinky-100MHz
-390e9530c93f57868311aa2ab69c67c4cce2226a 3-systick-blinky
-0000000000000000000000000000000000000000 3-systick-blinky
+++ /dev/null
-/**************************************************************************//**\r
- * @file LPC17xx.h\r
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for\r
- * NXP LPC17xx Device Series\r
- * @version V1.07\r
- * @date 19. October 2009\r
- *\r
- * @note\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
- * processor based microcontrollers. This file can be freely distributed\r
- * within development tools that are supporting such ARM based processors.\r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-\r
-#ifndef __LPC17xx_H__\r
-#define __LPC17xx_H__\r
-\r
-/*\r
- * ==========================================================================\r
- * ---------- Interrupt Number Definition -----------------------------------\r
- * ==========================================================================\r
- */\r
-\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
-\r
-/****** LPC17xx Specific Interrupt Numbers *******************************************************/\r
- WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */\r
- TIMER0_IRQn = 1, /*!< Timer0 Interrupt */\r
- TIMER1_IRQn = 2, /*!< Timer1 Interrupt */\r
- TIMER2_IRQn = 3, /*!< Timer2 Interrupt */\r
- TIMER3_IRQn = 4, /*!< Timer3 Interrupt */\r
- UART0_IRQn = 5, /*!< UART0 Interrupt */\r
- UART1_IRQn = 6, /*!< UART1 Interrupt */\r
- UART2_IRQn = 7, /*!< UART2 Interrupt */\r
- UART3_IRQn = 8, /*!< UART3 Interrupt */\r
- PWM1_IRQn = 9, /*!< PWM1 Interrupt */\r
- I2C0_IRQn = 10, /*!< I2C0 Interrupt */\r
- I2C1_IRQn = 11, /*!< I2C1 Interrupt */\r
- I2C2_IRQn = 12, /*!< I2C2 Interrupt */\r
- SPI_IRQn = 13, /*!< SPI Interrupt */\r
- SSP0_IRQn = 14, /*!< SSP0 Interrupt */\r
- SSP1_IRQn = 15, /*!< SSP1 Interrupt */\r
- PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */\r
- RTC_IRQn = 17, /*!< Real Time Clock Interrupt */\r
- EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */\r
- EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */\r
- EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */\r
- EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */\r
- ADC_IRQn = 22, /*!< A/D Converter Interrupt */\r
- BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */\r
- USB_IRQn = 24, /*!< USB Interrupt */\r
- CAN_IRQn = 25, /*!< CAN Interrupt */\r
- DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */\r
- I2S_IRQn = 27, /*!< I2S Interrupt */\r
- ENET_IRQn = 28, /*!< Ethernet Interrupt */\r
- RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */\r
- MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */\r
- QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */\r
- PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */\r
- USBActivity_IRQn = 33, /*!< USB Activity Interrupt */\r
- CANActivity_IRQn = 34, /*!< CAN Activity Interrupt */\r
-} IRQn_Type;\r
-\r
-\r
-/*\r
- * ==========================================================================\r
- * ----------- Processor and Core Peripheral Section ------------------------\r
- * ==========================================================================\r
- */\r
-\r
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */\r
-#define __MPU_PRESENT 1 /*!< MPU present or not */\r
-#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */\r
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
-\r
-\r
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */\r
-#include "system_LPC17xx.h" /* System Header */\r
-\r
-\r
-/******************************************************************************/\r
-/* Device Specific Peripheral registers structures */\r
-/******************************************************************************/\r
-\r
-#if defined ( __CC_ARM )\r
-#pragma anon_unions\r
-#endif\r
-\r
-/*------------- System Control (SC) ------------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t FLASHCFG; /* Flash Accelerator Module */\r
- uint32_t RESERVED0[31];\r
- __IO uint32_t PLL0CON; /* Clocking and Power Control */\r
- __IO uint32_t PLL0CFG;\r
- __I uint32_t PLL0STAT;\r
- __O uint32_t PLL0FEED;\r
- uint32_t RESERVED1[4];\r
- __IO uint32_t PLL1CON;\r
- __IO uint32_t PLL1CFG;\r
- __I uint32_t PLL1STAT;\r
- __O uint32_t PLL1FEED;\r
- uint32_t RESERVED2[4];\r
- __IO uint32_t PCON;\r
- __IO uint32_t PCONP;\r
- uint32_t RESERVED3[15];\r
- __IO uint32_t CCLKCFG;\r
- __IO uint32_t USBCLKCFG;\r
- __IO uint32_t CLKSRCSEL;\r
- uint32_t RESERVED4[12];\r
- __IO uint32_t EXTINT; /* External Interrupts */\r
- uint32_t RESERVED5;\r
- __IO uint32_t EXTMODE;\r
- __IO uint32_t EXTPOLAR;\r
- uint32_t RESERVED6[12];\r
- __IO uint32_t RSID; /* Reset */\r
- uint32_t RESERVED7[7];\r
- __IO uint32_t SCS; /* Syscon Miscellaneous Registers */\r
- __IO uint32_t IRCTRIM; /* Clock Dividers */\r
- __IO uint32_t PCLKSEL0;\r
- __IO uint32_t PCLKSEL1;\r
- uint32_t RESERVED8[4];\r
- __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */\r
- __IO uint32_t DMAREQSEL;\r
- __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */\r
- } LPC_SC_TypeDef;\r
-\r
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t PINSEL0;\r
- __IO uint32_t PINSEL1;\r
- __IO uint32_t PINSEL2;\r
- __IO uint32_t PINSEL3;\r
- __IO uint32_t PINSEL4;\r
- __IO uint32_t PINSEL5;\r
- __IO uint32_t PINSEL6;\r
- __IO uint32_t PINSEL7;\r
- __IO uint32_t PINSEL8;\r
- __IO uint32_t PINSEL9;\r
- __IO uint32_t PINSEL10;\r
- uint32_t RESERVED0[5];\r
- __IO uint32_t PINMODE0;\r
- __IO uint32_t PINMODE1;\r
- __IO uint32_t PINMODE2;\r
- __IO uint32_t PINMODE3;\r
- __IO uint32_t PINMODE4;\r
- __IO uint32_t PINMODE5;\r
- __IO uint32_t PINMODE6;\r
- __IO uint32_t PINMODE7;\r
- __IO uint32_t PINMODE8;\r
- __IO uint32_t PINMODE9;\r
- __IO uint32_t PINMODE_OD0;\r
- __IO uint32_t PINMODE_OD1;\r
- __IO uint32_t PINMODE_OD2;\r
- __IO uint32_t PINMODE_OD3;\r
- __IO uint32_t PINMODE_OD4;\r
- __IO uint32_t I2CPADCFG;\r
-} LPC_PINCON_TypeDef;\r
-\r
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/\r
-typedef struct\r
-{\r
- union {\r
- __IO uint32_t FIODIR;\r
- struct {\r
- __IO uint16_t FIODIRL;\r
- __IO uint16_t FIODIRH;\r
- };\r
- struct {\r
- __IO uint8_t FIODIR0;\r
- __IO uint8_t FIODIR1;\r
- __IO uint8_t FIODIR2;\r
- __IO uint8_t FIODIR3;\r
- };\r
- };\r
- uint32_t RESERVED0[3];\r
- union {\r
- __IO uint32_t FIOMASK;\r
- struct {\r
- __IO uint16_t FIOMASKL;\r
- __IO uint16_t FIOMASKH;\r
- };\r
- struct {\r
- __IO uint8_t FIOMASK0;\r
- __IO uint8_t FIOMASK1;\r
- __IO uint8_t FIOMASK2;\r
- __IO uint8_t FIOMASK3;\r
- };\r
- };\r
- union {\r
- __IO uint32_t FIOPIN;\r
- struct {\r
- __IO uint16_t FIOPINL;\r
- __IO uint16_t FIOPINH;\r
- };\r
- struct {\r
- __IO uint8_t FIOPIN0;\r
- __IO uint8_t FIOPIN1;\r
- __IO uint8_t FIOPIN2;\r
- __IO uint8_t FIOPIN3;\r
- };\r
- };\r
- union {\r
- __IO uint32_t FIOSET;\r
- struct {\r
- __IO uint16_t FIOSETL;\r
- __IO uint16_t FIOSETH;\r
- };\r
- struct {\r
- __IO uint8_t FIOSET0;\r
- __IO uint8_t FIOSET1;\r
- __IO uint8_t FIOSET2;\r
- __IO uint8_t FIOSET3;\r
- };\r
- };\r
- union {\r
- __O uint32_t FIOCLR;\r
- struct {\r
- __O uint16_t FIOCLRL;\r
- __O uint16_t FIOCLRH;\r
- };\r
- struct {\r
- __O uint8_t FIOCLR0;\r
- __O uint8_t FIOCLR1;\r
- __O uint8_t FIOCLR2;\r
- __O uint8_t FIOCLR3;\r
- };\r
- };\r
-} LPC_GPIO_TypeDef;\r
-\r
-typedef struct\r
-{\r
- __I uint32_t IntStatus;\r
- __I uint32_t IO0IntStatR;\r
- __I uint32_t IO0IntStatF;\r
- __O uint32_t IO0IntClr;\r
- __IO uint32_t IO0IntEnR;\r
- __IO uint32_t IO0IntEnF;\r
- uint32_t RESERVED0[3];\r
- __I uint32_t IO2IntStatR;\r
- __I uint32_t IO2IntStatF;\r
- __O uint32_t IO2IntClr;\r
- __IO uint32_t IO2IntEnR;\r
- __IO uint32_t IO2IntEnF;\r
-} LPC_GPIOINT_TypeDef;\r
-\r
-/*------------- Timer (TIM) --------------------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t IR;\r
- __IO uint32_t TCR;\r
- __IO uint32_t TC;\r
- __IO uint32_t PR;\r
- __IO uint32_t PC;\r
- __IO uint32_t MCR;\r
- __IO uint32_t MR0;\r
- __IO uint32_t MR1;\r
- __IO uint32_t MR2;\r
- __IO uint32_t MR3;\r
- __IO uint32_t CCR;\r
- __I uint32_t CR0;\r
- __I uint32_t CR1;\r
- uint32_t RESERVED0[2];\r
- __IO uint32_t EMR;\r
- uint32_t RESERVED1[12];\r
- __IO uint32_t CTCR;\r
-} LPC_TIM_TypeDef;\r
-\r
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t IR;\r
- __IO uint32_t TCR;\r
- __IO uint32_t TC;\r
- __IO uint32_t PR;\r
- __IO uint32_t PC;\r
- __IO uint32_t MCR;\r
- __IO uint32_t MR0;\r
- __IO uint32_t MR1;\r
- __IO uint32_t MR2;\r
- __IO uint32_t MR3;\r
- __IO uint32_t CCR;\r
- __I uint32_t CR0;\r
- __I uint32_t CR1;\r
- __I uint32_t CR2;\r
- __I uint32_t CR3;\r
- uint32_t RESERVED0;\r
- __IO uint32_t MR4;\r
- __IO uint32_t MR5;\r
- __IO uint32_t MR6;\r
- __IO uint32_t PCR;\r
- __IO uint32_t LER;\r
- uint32_t RESERVED1[7];\r
- __IO uint32_t CTCR;\r
-} LPC_PWM_TypeDef;\r
-\r
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/\r
-typedef struct\r
-{\r
- union {\r
- __I uint8_t RBR;\r
- __O uint8_t THR;\r
- __IO uint8_t DLL;\r
- uint32_t RESERVED0;\r
- };\r
- union {\r
- __IO uint8_t DLM;\r
- __IO uint32_t IER;\r
- };\r
- union {\r
- __I uint32_t IIR;\r
- __O uint8_t FCR;\r
- };\r
- __IO uint8_t LCR;\r
- uint8_t RESERVED1[7];\r
- __I uint8_t LSR;\r
- uint8_t RESERVED2[7];\r
- __IO uint8_t SCR;\r
- uint8_t RESERVED3[3];\r
- __IO uint32_t ACR;\r
- __IO uint8_t ICR;\r
- uint8_t RESERVED4[3];\r
- __IO uint8_t FDR;\r
- uint8_t RESERVED5[7];\r
- __IO uint8_t TER;\r
- uint8_t RESERVED6[39];\r
- __I uint8_t FIFOLVL;\r
-} LPC_UART_TypeDef;\r
-\r
-typedef struct\r
-{\r
- union {\r
- __I uint8_t RBR;\r
- __O uint8_t THR;\r
- __IO uint8_t DLL;\r
- uint32_t RESERVED0;\r
- };\r
- union {\r
- __IO uint8_t DLM;\r
- __IO uint32_t IER;\r
- };\r
- union {\r
- __I uint32_t IIR;\r
- __O uint8_t FCR;\r
- };\r
- __IO uint8_t LCR;\r
- uint8_t RESERVED1[7];\r
- __I uint8_t LSR;\r
- uint8_t RESERVED2[7];\r
- __IO uint8_t SCR;\r
- uint8_t RESERVED3[3];\r
- __IO uint32_t ACR;\r
- __IO uint8_t ICR;\r
- uint8_t RESERVED4[3];\r
- __IO uint8_t FDR;\r
- uint8_t RESERVED5[7];\r
- __IO uint8_t TER;\r
- uint8_t RESERVED6[39];\r
- __I uint8_t FIFOLVL;\r
-} LPC_UART0_TypeDef;\r
-\r
-typedef struct\r
-{\r
- union {\r
- __I uint8_t RBR;\r
- __O uint8_t THR;\r
- __IO uint8_t DLL;\r
- uint32_t RESERVED0;\r
- };\r
- union {\r
- __IO uint8_t DLM;\r
- __IO uint32_t IER;\r
- };\r
- union {\r
- __I uint32_t IIR;\r
- __O uint8_t FCR;\r
- };\r
- __IO uint8_t LCR;\r
- uint8_t RESERVED1[3];\r
- __IO uint8_t MCR;\r
- uint8_t RESERVED2[3];\r
- __I uint8_t LSR;\r
- uint8_t RESERVED3[3];\r
- __I uint8_t MSR;\r
- uint8_t RESERVED4[3];\r
- __IO uint8_t SCR;\r
- uint8_t RESERVED5[3];\r
- __IO uint32_t ACR;\r
- uint32_t RESERVED6;\r
- __IO uint32_t FDR;\r
- uint32_t RESERVED7;\r
- __IO uint8_t TER;\r
- uint8_t RESERVED8[27];\r
- __IO uint8_t RS485CTRL;\r
- uint8_t RESERVED9[3];\r
- __IO uint8_t ADRMATCH;\r
- uint8_t RESERVED10[3];\r
- __IO uint8_t RS485DLY;\r
- uint8_t RESERVED11[3];\r
- __I uint8_t FIFOLVL;\r
-} LPC_UART1_TypeDef;\r
-\r
-/*------------- Serial Peripheral Interface (SPI) ----------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t SPCR;\r
- __I uint32_t SPSR;\r
- __IO uint32_t SPDR;\r
- __IO uint32_t SPCCR;\r
- uint32_t RESERVED0[3];\r
- __IO uint32_t SPINT;\r
-} LPC_SPI_TypeDef;\r
-\r
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t CR0;\r
- __IO uint32_t CR1;\r
- __IO uint32_t DR;\r
- __I uint32_t SR;\r
- __IO uint32_t CPSR;\r
- __IO uint32_t IMSC;\r
- __IO uint32_t RIS;\r
- __IO uint32_t MIS;\r
- __IO uint32_t ICR;\r
- __IO uint32_t DMACR;\r
-} LPC_SSP_TypeDef;\r
-\r
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t I2CONSET;\r
- __I uint32_t I2STAT;\r
- __IO uint32_t I2DAT;\r
- __IO uint32_t I2ADR0;\r
- __IO uint32_t I2SCLH;\r
- __IO uint32_t I2SCLL;\r
- __O uint32_t I2CONCLR;\r
- __IO uint32_t MMCTRL;\r
- __IO uint32_t I2ADR1;\r
- __IO uint32_t I2ADR2;\r
- __IO uint32_t I2ADR3;\r
- __I uint32_t I2DATA_BUFFER;\r
- __IO uint32_t I2MASK0;\r
- __IO uint32_t I2MASK1;\r
- __IO uint32_t I2MASK2;\r
- __IO uint32_t I2MASK3;\r
-} LPC_I2C_TypeDef;\r
-\r
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t I2SDAO;\r
- __IO uint32_t I2SDAI;\r
- __O uint32_t I2STXFIFO;\r
- __I uint32_t I2SRXFIFO;\r
- __I uint32_t I2SSTATE;\r
- __IO uint32_t I2SDMA1;\r
- __IO uint32_t I2SDMA2;\r
- __IO uint32_t I2SIRQ;\r
- __IO uint32_t I2STXRATE;\r
- __IO uint32_t I2SRXRATE;\r
- __IO uint32_t I2STXBITRATE;\r
- __IO uint32_t I2SRXBITRATE;\r
- __IO uint32_t I2STXMODE;\r
- __IO uint32_t I2SRXMODE;\r
-} LPC_I2S_TypeDef;\r
-\r
-/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t RICOMPVAL;\r
- __IO uint32_t RIMASK;\r
- __IO uint8_t RICTRL;\r
- uint8_t RESERVED0[3];\r
- __IO uint32_t RICOUNTER;\r
-} LPC_RIT_TypeDef;\r
-\r
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint8_t ILR;\r
- uint8_t RESERVED0[7];\r
- __IO uint8_t CCR;\r
- uint8_t RESERVED1[3];\r
- __IO uint8_t CIIR;\r
- uint8_t RESERVED2[3];\r
- __IO uint8_t AMR;\r
- uint8_t RESERVED3[3];\r
- __I uint32_t CTIME0;\r
- __I uint32_t CTIME1;\r
- __I uint32_t CTIME2;\r
- __IO uint8_t SEC;\r
- uint8_t RESERVED4[3];\r
- __IO uint8_t MIN;\r
- uint8_t RESERVED5[3];\r
- __IO uint8_t HOUR;\r
- uint8_t RESERVED6[3];\r
- __IO uint8_t DOM;\r
- uint8_t RESERVED7[3];\r
- __IO uint8_t DOW;\r
- uint8_t RESERVED8[3];\r
- __IO uint16_t DOY;\r
- uint16_t RESERVED9;\r
- __IO uint8_t MONTH;\r
- uint8_t RESERVED10[3];\r
- __IO uint16_t YEAR;\r
- uint16_t RESERVED11;\r
- __IO uint32_t CALIBRATION;\r
- __IO uint32_t GPREG0;\r
- __IO uint32_t GPREG1;\r
- __IO uint32_t GPREG2;\r
- __IO uint32_t GPREG3;\r
- __IO uint32_t GPREG4;\r
- __IO uint8_t RTC_AUXEN;\r
- uint8_t RESERVED12[3];\r
- __IO uint8_t RTC_AUX;\r
- uint8_t RESERVED13[3];\r
- __IO uint8_t ALSEC;\r
- uint8_t RESERVED14[3];\r
- __IO uint8_t ALMIN;\r
- uint8_t RESERVED15[3];\r
- __IO uint8_t ALHOUR;\r
- uint8_t RESERVED16[3];\r
- __IO uint8_t ALDOM;\r
- uint8_t RESERVED17[3];\r
- __IO uint8_t ALDOW;\r
- uint8_t RESERVED18[3];\r
- __IO uint16_t ALDOY;\r
- uint16_t RESERVED19;\r
- __IO uint8_t ALMON;\r
- uint8_t RESERVED20[3];\r
- __IO uint16_t ALYEAR;\r
- uint16_t RESERVED21;\r
-} LPC_RTC_TypeDef;\r
-\r
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint8_t WDMOD;\r
- uint8_t RESERVED0[3];\r
- __IO uint32_t WDTC;\r
- __O uint8_t WDFEED;\r
- uint8_t RESERVED1[3];\r
- __I uint32_t WDTV;\r
- __IO uint32_t WDCLKSEL;\r
-} LPC_WDT_TypeDef;\r
-\r
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t ADCR;\r
- __IO uint32_t ADGDR;\r
- uint32_t RESERVED0;\r
- __IO uint32_t ADINTEN;\r
- __I uint32_t ADDR0;\r
- __I uint32_t ADDR1;\r
- __I uint32_t ADDR2;\r
- __I uint32_t ADDR3;\r
- __I uint32_t ADDR4;\r
- __I uint32_t ADDR5;\r
- __I uint32_t ADDR6;\r
- __I uint32_t ADDR7;\r
- __I uint32_t ADSTAT;\r
- __IO uint32_t ADTRM;\r
-} LPC_ADC_TypeDef;\r
-\r
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t DACR;\r
- __IO uint32_t DACCTRL;\r
- __IO uint16_t DACCNTVAL;\r
-} LPC_DAC_TypeDef;\r
-\r
-/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/\r
-typedef struct\r
-{\r
- __I uint32_t MCCON;\r
- __O uint32_t MCCON_SET;\r
- __O uint32_t MCCON_CLR;\r
- __I uint32_t MCCAPCON;\r
- __O uint32_t MCCAPCON_SET;\r
- __O uint32_t MCCAPCON_CLR;\r
- __IO uint32_t MCTIM0;\r
- __IO uint32_t MCTIM1;\r
- __IO uint32_t MCTIM2;\r
- __IO uint32_t MCPER0;\r
- __IO uint32_t MCPER1;\r
- __IO uint32_t MCPER2;\r
- __IO uint32_t MCPW0;\r
- __IO uint32_t MCPW1;\r
- __IO uint32_t MCPW2;\r
- __IO uint32_t MCDEADTIME;\r
- __IO uint32_t MCCCP;\r
- __IO uint32_t MCCR0;\r
- __IO uint32_t MCCR1;\r
- __IO uint32_t MCCR2;\r
- __I uint32_t MCINTEN;\r
- __O uint32_t MCINTEN_SET;\r
- __O uint32_t MCINTEN_CLR;\r
- __I uint32_t MCCNTCON;\r
- __O uint32_t MCCNTCON_SET;\r
- __O uint32_t MCCNTCON_CLR;\r
- __I uint32_t MCINTFLAG;\r
- __O uint32_t MCINTFLAG_SET;\r
- __O uint32_t MCINTFLAG_CLR;\r
- __O uint32_t MCCAP_CLR;\r
-} LPC_MCPWM_TypeDef;\r
-\r
-/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/\r
-typedef struct\r
-{\r
- __O uint32_t QEICON;\r
- __I uint32_t QEISTAT;\r
- __IO uint32_t QEICONF;\r
- __I uint32_t QEIPOS;\r
- __IO uint32_t QEIMAXPOS;\r
- __IO uint32_t CMPOS0;\r
- __IO uint32_t CMPOS1;\r
- __IO uint32_t CMPOS2;\r
- __I uint32_t INXCNT;\r
- __IO uint32_t INXCMP;\r
- __IO uint32_t QEILOAD;\r
- __I uint32_t QEITIME;\r
- __I uint32_t QEIVEL;\r
- __I uint32_t QEICAP;\r
- __IO uint32_t VELCOMP;\r
- __IO uint32_t FILTER;\r
- uint32_t RESERVED0[998];\r
- __O uint32_t QEIIEC;\r
- __O uint32_t QEIIES;\r
- __I uint32_t QEIINTSTAT;\r
- __I uint32_t QEIIE;\r
- __O uint32_t QEICLR;\r
- __O uint32_t QEISET;\r
-} LPC_QEI_TypeDef;\r
-\r
-/*------------- Controller Area Network (CAN) --------------------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t mask[512]; /* ID Masks */\r
-} LPC_CANAF_RAM_TypeDef;\r
-\r
-typedef struct /* Acceptance Filter Registers */\r
-{\r
- __IO uint32_t AFMR;\r
- __IO uint32_t SFF_sa;\r
- __IO uint32_t SFF_GRP_sa;\r
- __IO uint32_t EFF_sa;\r
- __IO uint32_t EFF_GRP_sa;\r
- __IO uint32_t ENDofTable;\r
- __I uint32_t LUTerrAd;\r
- __I uint32_t LUTerr;\r
- __IO uint32_t FCANIE;\r
- __IO uint32_t FCANIC0;\r
- __IO uint32_t FCANIC1;\r
-} LPC_CANAF_TypeDef;\r
-\r
-typedef struct /* Central Registers */\r
-{\r
- __I uint32_t CANTxSR;\r
- __I uint32_t CANRxSR;\r
- __I uint32_t CANMSR;\r
-} LPC_CANCR_TypeDef;\r
-\r
-typedef struct /* Controller Registers */\r
-{\r
- __IO uint32_t MOD;\r
- __O uint32_t CMR;\r
- __IO uint32_t GSR;\r
- __I uint32_t ICR;\r
- __IO uint32_t IER;\r
- __IO uint32_t BTR;\r
- __IO uint32_t EWL;\r
- __I uint32_t SR;\r
- __IO uint32_t RFS;\r
- __IO uint32_t RID;\r
- __IO uint32_t RDA;\r
- __IO uint32_t RDB;\r
- __IO uint32_t TFI1;\r
- __IO uint32_t TID1;\r
- __IO uint32_t TDA1;\r
- __IO uint32_t TDB1;\r
- __IO uint32_t TFI2;\r
- __IO uint32_t TID2;\r
- __IO uint32_t TDA2;\r
- __IO uint32_t TDB2;\r
- __IO uint32_t TFI3;\r
- __IO uint32_t TID3;\r
- __IO uint32_t TDA3;\r
- __IO uint32_t TDB3;\r
-} LPC_CAN_TypeDef;\r
-\r
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/\r
-typedef struct /* Common Registers */\r
-{\r
- __I uint32_t DMACIntStat;\r
- __I uint32_t DMACIntTCStat;\r
- __O uint32_t DMACIntTCClear;\r
- __I uint32_t DMACIntErrStat;\r
- __O uint32_t DMACIntErrClr;\r
- __I uint32_t DMACRawIntTCStat;\r
- __I uint32_t DMACRawIntErrStat;\r
- __I uint32_t DMACEnbldChns;\r
- __IO uint32_t DMACSoftBReq;\r
- __IO uint32_t DMACSoftSReq;\r
- __IO uint32_t DMACSoftLBReq;\r
- __IO uint32_t DMACSoftLSReq;\r
- __IO uint32_t DMACConfig;\r
- __IO uint32_t DMACSync;\r
-} LPC_GPDMA_TypeDef;\r
-\r
-typedef struct /* Channel Registers */\r
-{\r
- __IO uint32_t DMACCSrcAddr;\r
- __IO uint32_t DMACCDestAddr;\r
- __IO uint32_t DMACCLLI;\r
- __IO uint32_t DMACCControl;\r
- __IO uint32_t DMACCConfig;\r
-} LPC_GPDMACH_TypeDef;\r
-\r
-/*------------- Universal Serial Bus (USB) -----------------------------------*/\r
-typedef struct\r
-{\r
- __I uint32_t HcRevision; /* USB Host Registers */\r
- __IO uint32_t HcControl;\r
- __IO uint32_t HcCommandStatus;\r
- __IO uint32_t HcInterruptStatus;\r
- __IO uint32_t HcInterruptEnable;\r
- __IO uint32_t HcInterruptDisable;\r
- __IO uint32_t HcHCCA;\r
- __I uint32_t HcPeriodCurrentED;\r
- __IO uint32_t HcControlHeadED;\r
- __IO uint32_t HcControlCurrentED;\r
- __IO uint32_t HcBulkHeadED;\r
- __IO uint32_t HcBulkCurrentED;\r
- __I uint32_t HcDoneHead;\r
- __IO uint32_t HcFmInterval;\r
- __I uint32_t HcFmRemaining;\r
- __I uint32_t HcFmNumber;\r
- __IO uint32_t HcPeriodicStart;\r
- __IO uint32_t HcLSTreshold;\r
- __IO uint32_t HcRhDescriptorA;\r
- __IO uint32_t HcRhDescriptorB;\r
- __IO uint32_t HcRhStatus;\r
- __IO uint32_t HcRhPortStatus1;\r
- __IO uint32_t HcRhPortStatus2;\r
- uint32_t RESERVED0[40];\r
- __I uint32_t Module_ID;\r
-\r
- __I uint32_t OTGIntSt; /* USB On-The-Go Registers */\r
- __IO uint32_t OTGIntEn;\r
- __O uint32_t OTGIntSet;\r
- __O uint32_t OTGIntClr;\r
- __IO uint32_t OTGStCtrl;\r
- __IO uint32_t OTGTmr;\r
- uint32_t RESERVED1[58];\r
-\r
- __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */\r
- __IO uint32_t USBDevIntEn;\r
- __O uint32_t USBDevIntClr;\r
- __O uint32_t USBDevIntSet;\r
-\r
- __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */\r
- __I uint32_t USBCmdData;\r
-\r
- __I uint32_t USBRxData; /* USB Device Transfer Registers */\r
- __O uint32_t USBTxData;\r
- __I uint32_t USBRxPLen;\r
- __O uint32_t USBTxPLen;\r
- __IO uint32_t USBCtrl;\r
- __O uint32_t USBDevIntPri;\r
-\r
- __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */\r
- __IO uint32_t USBEpIntEn;\r
- __O uint32_t USBEpIntClr;\r
- __O uint32_t USBEpIntSet;\r
- __O uint32_t USBEpIntPri;\r
-\r
- __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/\r
- __O uint32_t USBEpInd;\r
- __IO uint32_t USBMaxPSize;\r
-\r
- __I uint32_t USBDMARSt; /* USB Device DMA Registers */\r
- __O uint32_t USBDMARClr;\r
- __O uint32_t USBDMARSet;\r
- uint32_t RESERVED2[9];\r
- __IO uint32_t USBUDCAH;\r
- __I uint32_t USBEpDMASt;\r
- __O uint32_t USBEpDMAEn;\r
- __O uint32_t USBEpDMADis;\r
- __I uint32_t USBDMAIntSt;\r
- __IO uint32_t USBDMAIntEn;\r
- uint32_t RESERVED3[2];\r
- __I uint32_t USBEoTIntSt;\r
- __O uint32_t USBEoTIntClr;\r
- __O uint32_t USBEoTIntSet;\r
- __I uint32_t USBNDDRIntSt;\r
- __O uint32_t USBNDDRIntClr;\r
- __O uint32_t USBNDDRIntSet;\r
- __I uint32_t USBSysErrIntSt;\r
- __O uint32_t USBSysErrIntClr;\r
- __O uint32_t USBSysErrIntSet;\r
- uint32_t RESERVED4[15];\r
-\r
- __I uint32_t I2C_RX; /* USB OTG I2C Registers */\r
- __O uint32_t I2C_WO;\r
- __I uint32_t I2C_STS;\r
- __IO uint32_t I2C_CTL;\r
- __IO uint32_t I2C_CLKHI;\r
- __O uint32_t I2C_CLKLO;\r
- uint32_t RESERVED5[823];\r
-\r
- union {\r
- __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */\r
- __IO uint32_t OTGClkCtrl;\r
- };\r
- union {\r
- __I uint32_t USBClkSt;\r
- __I uint32_t OTGClkSt;\r
- };\r
-} LPC_USB_TypeDef;\r
-\r
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/\r
-typedef struct\r
-{\r
- __IO uint32_t MAC1; /* MAC Registers */\r
- __IO uint32_t MAC2;\r
- __IO uint32_t IPGT;\r
- __IO uint32_t IPGR;\r
- __IO uint32_t CLRT;\r
- __IO uint32_t MAXF;\r
- __IO uint32_t SUPP;\r
- __IO uint32_t TEST;\r
- __IO uint32_t MCFG;\r
- __IO uint32_t MCMD;\r
- __IO uint32_t MADR;\r
- __O uint32_t MWTD;\r
- __I uint32_t MRDD;\r
- __I uint32_t MIND;\r
- uint32_t RESERVED0[2];\r
- __IO uint32_t SA0;\r
- __IO uint32_t SA1;\r
- __IO uint32_t SA2;\r
- uint32_t RESERVED1[45];\r
- __IO uint32_t Command; /* Control Registers */\r
- __I uint32_t Status;\r
- __IO uint32_t RxDescriptor;\r
- __IO uint32_t RxStatus;\r
- __IO uint32_t RxDescriptorNumber;\r
- __I uint32_t RxProduceIndex;\r
- __IO uint32_t RxConsumeIndex;\r
- __IO uint32_t TxDescriptor;\r
- __IO uint32_t TxStatus;\r
- __IO uint32_t TxDescriptorNumber;\r
- __IO uint32_t TxProduceIndex;\r
- __I uint32_t TxConsumeIndex;\r
- uint32_t RESERVED2[10];\r
- __I uint32_t TSV0;\r
- __I uint32_t TSV1;\r
- __I uint32_t RSV;\r
- uint32_t RESERVED3[3];\r
- __IO uint32_t FlowControlCounter;\r
- __I uint32_t FlowControlStatus;\r
- uint32_t RESERVED4[34];\r
- __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */\r
- __IO uint32_t RxFilterWoLStatus;\r
- __IO uint32_t RxFilterWoLClear;\r
- uint32_t RESERVED5;\r
- __IO uint32_t HashFilterL;\r
- __IO uint32_t HashFilterH;\r
- uint32_t RESERVED6[882];\r
- __I uint32_t IntStatus; /* Module Control Registers */\r
- __IO uint32_t IntEnable;\r
- __O uint32_t IntClear;\r
- __O uint32_t IntSet;\r
- uint32_t RESERVED7;\r
- __IO uint32_t PowerDown;\r
- uint32_t RESERVED8;\r
- __IO uint32_t Module_ID;\r
-} LPC_EMAC_TypeDef;\r
-\r
-#if defined ( __CC_ARM )\r
-#pragma no_anon_unions\r
-#endif\r
-\r
-\r
-/******************************************************************************/\r
-/* Peripheral memory map */\r
-/******************************************************************************/\r
-/* Base addresses */\r
-#define LPC_FLASH_BASE (0x00000000UL)\r
-#define LPC_RAM_BASE (0x10000000UL)\r
-#ifdef __LPC17XX_REV00\r
-#define LPC_AHBRAM0_BASE (0x20000000UL)\r
-#define LPC_AHBRAM1_BASE (0x20004000UL)\r
-#else\r
-#define LPC_AHBRAM0_BASE (0x2007C000UL)\r
-#define LPC_AHBRAM1_BASE (0x20080000UL)\r
-#endif\r
-#define LPC_GPIO_BASE (0x2009C000UL)\r
-#define LPC_APB0_BASE (0x40000000UL)\r
-#define LPC_APB1_BASE (0x40080000UL)\r
-#define LPC_AHB_BASE (0x50000000UL)\r
-#define LPC_CM3_BASE (0xE0000000UL)\r
-\r
-/* APB0 peripherals */\r
-#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)\r
-#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)\r
-#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)\r
-#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)\r
-#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)\r
-#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)\r
-#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)\r
-#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)\r
-#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)\r
-#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)\r
-#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)\r
-#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)\r
-#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)\r
-#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)\r
-#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)\r
-#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)\r
-#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)\r
-#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)\r
-#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)\r
-\r
-/* APB1 peripherals */\r
-#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)\r
-#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)\r
-#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)\r
-#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)\r
-#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)\r
-#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)\r
-#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)\r
-#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)\r
-#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)\r
-#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)\r
-#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)\r
-#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)\r
-\r
-/* AHB peripherals */\r
-#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)\r
-#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)\r
-#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)\r
-#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)\r
-#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)\r
-#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)\r
-#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)\r
-#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)\r
-#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)\r
-#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)\r
-#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)\r
-\r
-/* GPIOs */\r
-#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)\r
-#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)\r
-#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)\r
-#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)\r
-#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)\r
-\r
-\r
-/******************************************************************************/\r
-/* Peripheral declaration */\r
-/******************************************************************************/\r
-#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )\r
-#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )\r
-#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )\r
-#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )\r
-#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )\r
-#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )\r
-#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )\r
-#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )\r
-#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )\r
-#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )\r
-#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )\r
-#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )\r
-#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )\r
-#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )\r
-#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )\r
-#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )\r
-#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )\r
-#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )\r
-#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )\r
-#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )\r
-#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )\r
-#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )\r
-#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )\r
-#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )\r
-#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )\r
-#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )\r
-#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )\r
-#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )\r
-#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )\r
-#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)\r
-#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )\r
-#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )\r
-#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )\r
-#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )\r
-#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )\r
-#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )\r
-#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )\r
-#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )\r
-#define DMAREQSEL (*(__IO uint32_t *) ( 0x4000C1C4))\r
-#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )\r
-#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )\r
-#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )\r
-#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )\r
-#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )\r
-#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )\r
-#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )\r
-#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )\r
-#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )\r
-\r
-#endif // __LPC17xx_H__\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm3.h\r
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version V1.30\r
- * @date 30. October 2009\r
- *\r
- * @note\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
- * processor based microcontrollers. This file can be freely distributed\r
- * within development tools that are supporting such ARM based processors.\r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-#ifndef __CM3_CORE_H__\r
-#define __CM3_CORE_H__\r
-\r
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
- *\r
- * List of Lint messages which will be suppressed and not shown:\r
- * - Error 10: \n\r
- * register uint32_t __regBasePri __asm("basepri"); \n\r
- * Error 10: Expecting ';'\r
- * .\r
- * - Error 530: \n\r
- * return(__regBasePri); \n\r
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
- * .\r
- * - Error 550: \n\r
- * __regBasePri = (basePri & 0x1ff); \n\r
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
- * .\r
- * - Error 754: \n\r
- * uint32_t RESERVED0[24]; \n\r
- * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
- * .\r
- * - Error 750: \n\r
- * #define __CM3_CORE_H__ \n\r
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
- * .\r
- * - Error 528: \n\r
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
- * .\r
- * - Error 751: \n\r
- * } InterruptType_Type; \n\r
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
- * .\r
- * Note: To re-enable a Message, insert a space before 'lint' *\r
- *\r
- */\r
-\r
-/*lint -save */\r
-/*lint -e10 */\r
-/*lint -e530 */\r
-/*lint -e550 */\r
-/*lint -e754 */\r
-/*lint -e750 */\r
-/*lint -e528 */\r
-/*lint -e751 */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
- This file defines all structures and symbols for CMSIS core:\r
- - CMSIS version number\r
- - Cortex-M core registers and bitfields\r
- - Cortex-M core peripheral base address\r
- @{\r
- */\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x03) /*!< Cortex core */\r
-\r
-#include <stdint.h> /* Include standard types */\r
-\r
-#if defined (__ICCARM__)\r
- #include <intrinsics.h> /* IAR Intrinsics */\r
-#endif\r
-\r
-\r
-#ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
-#endif\r
-\r
-\r
-\r
-\r
-/**\r
- * IO definitions\r
- *\r
- * define access restrictions to peripheral registers\r
- */\r
-\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< defines 'write only' permissions */\r
-#define __IO volatile /*!< defines 'read / write' permissions */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- ******************************************************************************/\r
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
- @{\r
-*/\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24];\r
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24];\r
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24];\r
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24];\r
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */\r
- uint32_t RESERVED4[56];\r
- __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644];\r
- __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
- memory mapped structure for System Control Block (SCB)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */\r
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */\r
- __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */\r
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */\r
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */\r
- __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */\r
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */\r
- __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */\r
- __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */\r
- __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */\r
- __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */\r
- __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */\r
- __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */\r
- __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
-#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
-\r
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
-\r
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
-\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
-\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
-\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
-\r
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
-\r
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
-\r
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
-\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
-\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
-\r
-/* SCB Configurable Fault Status Registers Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
-\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
-\r
-/* SCB Hard Fault Status Registers Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
-\r
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
-\r
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
-\r
-/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
-\r
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
-\r
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
-\r
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
-\r
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_SCB */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
- memory mapped structure for SysTick\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
- memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __O union\r
- {\r
- __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864];\r
- __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */\r
- uint32_t RESERVED1[15];\r
- __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15];\r
- __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */\r
- uint32_t RESERVED3[29];\r
- __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */\r
- __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */\r
- __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43];\r
- __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */\r
- __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */\r
- uint32_t RESERVED5[6];\r
- __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */\r
- __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */\r
- __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */\r
- __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */\r
- __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */\r
- __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */\r
- __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */\r
- __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */\r
- __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */\r
- __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */\r
- __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */\r
- __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */\r
-} ITM_Type;\r
-\r
-/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
-\r
-/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
-\r
-#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */\r
-\r
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
-\r
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
-\r
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
-\r
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
-\r
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
-\r
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
-\r
-/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
-\r
-/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
-\r
-/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
-\r
-/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
-\r
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
-\r
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_ITM */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
- memory mapped structure for Interrupt Type\r
- @{\r
- */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0;\r
- __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */\r
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
- __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */\r
-#else\r
- uint32_t RESERVED1;\r
-#endif\r
-} InterruptType_Type;\r
-\r
-/* Interrupt Controller Type Register Definitions */\r
-#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */\r
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
-\r
-/* Auxiliary Control Register Definitions */\r
-#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */\r
-#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */\r
-\r
-#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
-\r
-#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */\r
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
-\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
- memory mapped structure for Memory Protection Unit (MPU)\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */\r
- __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */\r
- __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-\r
-/* MPU Type Register */\r
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
-\r
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
-\r
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
-\r
-/* MPU Control Register */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
-\r
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
-\r
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
-\r
-/* MPU Region Number Register */\r
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
-\r
-/* MPU Region Base Address Register */\r
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
-\r
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
-\r
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
-\r
-/* MPU Region Attribute and Size Register */\r
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */\r
-#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */\r
-\r
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */\r
-#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */\r
-\r
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */\r
-#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */\r
-\r
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */\r
-#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */\r
-\r
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */\r
-#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */\r
-\r
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */\r
-#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */\r
-\r
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
-\r
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
-\r
-#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_MPU */\r
-#endif\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
- memory mapped structure for Core Debug Register\r
- @{\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-/* Debug Halting Control and Status Register */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
-\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
-\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
-\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
-\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
-\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
-\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
-\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
-\r
-/* Debug Core Register Selector Register */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
-\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
-\r
-/* Debug Exception and Monitor Control Register */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
-\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
-\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
-\r
-\r
-/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
-\r
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_register */\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- ******************************************************************************/\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
-\r
-#endif\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#define __enable_fault_irq __enable_fiq\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-#define __NOP __nop\r
-#define __WFI __wfi\r
-#define __WFE __wfe\r
-#define __SEV __sev\r
-#define __ISB() __isb(0)\r
-#define __DSB() __dsb(0)\r
-#define __DMB() __dmb(0)\r
-#define __REV __rev\r
-#define __RBIT __rbit\r
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP\r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP\r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-\r
-#if (__ARMCC_VERSION < 400000)\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-extern void __CLREX(void);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- *\r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-#else /* (__ARMCC_VERSION >= 400000) */\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-#define __CLREX __clrex\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-static __INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-static __INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0xff);\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-static __INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-static __INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-static __INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & 1);\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- *\r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-static __INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-static __INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-#endif /* __ARMCC_VERSION */\r
-\r
-\r
-\r
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
-\r
-#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */\r
-static __INLINE void __WFI() { __ASM ("wfi"); }\r
-static __INLINE void __WFE() { __ASM ("wfe"); }\r
-static __INLINE void __SEV() { __ASM ("sev"); }\r
-static __INLINE void __CLREX() { __ASM ("clrex"); }\r
-\r
-/* intrinsic void __ISB(void) */\r
-/* intrinsic void __DSB(void) */\r
-/* intrinsic void __DMB(void) */\r
-/* intrinsic void __set_PRIMASK(); */\r
-/* intrinsic void __get_PRIMASK(); */\r
-/* intrinsic void __set_FAULTMASK(); */\r
-/* intrinsic void __get_FAULTMASK(); */\r
-/* intrinsic uint32_t __REV(uint32_t value); */\r
-/* intrinsic uint32_t __REVSH(uint32_t value); */\r
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
-/* intrinsic unsigned long __LDREX(unsigned long *); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP\r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP\r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit values)\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-\r
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }\r
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }\r
-\r
-static __INLINE void __NOP() { __ASM volatile ("nop"); }\r
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }\r
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }\r
-static __INLINE void __SEV() { __ASM volatile ("sev"); }\r
-static __INLINE void __ISB() { __ASM volatile ("isb"); }\r
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }\r
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }\r
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP\r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP\r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
-*\r
-* @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-/**\r
- * @brief Reverse byte order in integer value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in integer value\r
- */\r
-extern uint32_t __REV(uint32_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit value\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
- Core Function Interface containing:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Reset Functions\r
-*/\r
-/*@{*/\r
-\r
-/* ########################## NVIC functions #################################### */\r
-\r
-/**\r
- * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
- *\r
- * @param PriorityGroup is priority grouping field\r
- *\r
- * Set the priority grouping field using the required unlock sequence.\r
- * The parameter priority_grouping is assigned to the field\r
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- */\r
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
-\r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-/**\r
- * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
- *\r
- * @return priority grouping field\r
- *\r
- * Get the priority grouping from NVIC Interrupt Controller.\r
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
-}\r
-\r
-/**\r
- * @brief Enable Interrupt in NVIC Interrupt Controller\r
- *\r
- * @param IRQn The positive number of the external interrupt to enable\r
- *\r
- * Enable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Disable the interrupt line for external interrupt specified\r
- *\r
- * @param IRQn The positive number of the external interrupt to disable\r
- *\r
- * Disable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the interrupt pending bit for a device specific interrupt source\r
- *\r
- * @param IRQn The number of the device specifc interrupt\r
- * @return 1 = interrupt pending, 0 = interrupt not pending\r
- *\r
- * Read the pending register in NVIC and return 1 if its status is pending,\r
- * otherwise it returns 0\r
- */\r
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the pending bit for an external interrupt\r
- *\r
- * @param IRQn The number of the interrupt for set pending\r
- *\r
- * Set the pending bit for the specified interrupt.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
-}\r
-\r
-/**\r
- * @brief Clear the pending bit for an external interrupt\r
- *\r
- * @param IRQn The number of the interrupt for clear pending\r
- *\r
- * Clear the pending bit for the specified interrupt.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the active bit for an external interrupt\r
- *\r
- * @param IRQn The number of the interrupt for read active bit\r
- * @return 1 = interrupt active, 0 = interrupt not active\r
- *\r
- * Read the active register in NVIC and returns 1 if its status is active,\r
- * otherwise it returns 0.\r
- */\r
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the priority for an interrupt\r
- *\r
- * @param IRQn The number of the interrupt for set priority\r
- * @param priority The priority to set\r
- *\r
- * Set the priority for the specified interrupt. The interrupt\r
- * number can be positive to specify an external (device specific)\r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
- else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
-}\r
-\r
-/**\r
- * @brief Read the priority for an interrupt\r
- *\r
- * @param IRQn The number of the interrupt for get priority\r
- * @return The priority for the interrupt\r
- *\r
- * Read the priority for the specified interrupt. The interrupt\r
- * number can be positive to specify an external (device specific)\r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * The returned priority value is automatically aligned to the implemented\r
- * priority bits of the microcontroller.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
- else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
-}\r
-\r
-\r
-/**\r
- * @brief Encode the priority for an interrupt\r
- *\r
- * @param PriorityGroup The used priority group\r
- * @param PreemptPriority The preemptive priority value (starting from 0)\r
- * @param SubPriority The sub priority value (starting from 0)\r
- * @return The encoded priority for the interrupt\r
- *\r
- * Encode the priority for an interrupt with the given priority group,\r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The returned priority value can be used for NVIC_SetPriority(...) function\r
- */\r
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
-\r
- return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- * @brief Decode the priority of an interrupt\r
- *\r
- * @param Priority The priority for the interrupt\r
- * @param PriorityGroup The used priority group\r
- * @param pPreemptPriority The preemptive priority value (starting from 0)\r
- * @param pSubPriority The sub priority value (starting from 0)\r
- *\r
- * Decode an interrupt priority value with the given priority group to\r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The priority value can be retrieved with NVIC_GetPriority(...) function\r
- */\r
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
-\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
-}\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-\r
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
-\r
-/**\r
- * @brief Initialize and start the SysTick counter and its interrupt.\r
- *\r
- * @param ticks number of ticks between two interrupts\r
- * @return 1 = failed, 0 = successful\r
- *\r
- * Initialise the system tick timer and its interrupt and start the\r
- * system tick timer / counter in free running mode to generate\r
- * periodical interrupts.\r
- */\r
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
-\r
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-\r
-\r
-\r
-/* ################################## Reset function ############################################ */\r
-\r
-/**\r
- * @brief Initiate a system reset request.\r
- *\r
- * Initiate a system reset request to reset the MCU\r
- */\r
-static __INLINE void NVIC_SystemReset(void)\r
-{\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
-}\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
-\r
-\r
-\r
-/* ##################################### Debug In/Output function ########################################### */\r
-\r
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
- Core Debug Interface containing:\r
- - Core Debug Receive / Transmit Functions\r
- - Core Debug Defines\r
- - Core Debug Variables\r
-*/\r
-/*@{*/\r
-\r
-extern volatile int ITM_RxBuffer; /*!< variable to receive characters */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
-\r
-\r
-/**\r
- * @brief Outputs a character via the ITM channel 0\r
- *\r
- * @param ch character to output\r
- * @return character to output\r
- *\r
- * The function outputs a character via the ITM channel 0.\r
- * The function returns when no debugger is connected that has booked the output.\r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
- */\r
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */\r
- {\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
- }\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- * @brief Inputs a character via variable ITM_RxBuffer\r
- *\r
- * @return received character, -1 = no character received\r
- *\r
- * The function inputs a character via variable ITM_RxBuffer.\r
- * The function returns when no debugger is connected that has booked the output.\r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.\r
- */\r
-static __INLINE int ITM_ReceiveChar (void) {\r
- int ch = -1; /* no character available */\r
-\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
- ch = ITM_RxBuffer;\r
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
- }\r
-\r
- return (ch);\r
-}\r
-\r
-\r
-/**\r
- * @brief Check if a character via variable ITM_RxBuffer is available\r
- *\r
- * @return 1 = character available, 0 = no character available\r
- *\r
- * The function checks variable ITM_RxBuffer whether a character is available or not.\r
- * The function returns '1' if a character is available and '0' if no character is available.\r
- */\r
-static __INLINE int ITM_CheckChar (void) {\r
-\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
- return (0); /* no character available */\r
- } else {\r
- return (1); /* character available */\r
- }\r
-}\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
-\r
-#endif /* __CM3_CORE_H__ */\r
-\r
-/*lint -restore */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file system_LPC17xx.c\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File\r
- * for the NXP LPC17xx Device Series\r
- * @version V1.03\r
- * @date 07. October 2009\r
- *\r
- * @note\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
- * processor based microcontrollers. This file can be freely distributed\r
- * within development tools that are supporting such ARM based processors.\r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-\r
-#include <stdint.h>\r
-#include "LPC17xx.h"\r
-\r
-/*\r
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\r
-*/\r
-\r
-/*--------------------- Clock Configuration ----------------------------------\r
-//\r
-// <e> Clock Configuration\r
-// <h> System Controls and Status Register (SCS)\r
-// <o1.4> OSCRANGE: Main Oscillator Range Select\r
-// <0=> 1 MHz to 20 MHz\r
-// <1=> 15 MHz to 24 MHz\r
-// <e1.5> OSCEN: Main Oscillator Enable\r
-// </e>\r
-// </h>\r
-//\r
-// <h> Clock Source Select Register (CLKSRCSEL)\r
-// <o2.0..1> CLKSRC: PLL Clock Source Selection\r
-// <0=> Internal RC oscillator\r
-// <1=> Main oscillator\r
-// <2=> RTC oscillator\r
-// </h>\r
-//\r
-// <e3> PLL0 Configuration (Main PLL)\r
-// <h> PLL0 Configuration Register (PLL0CFG)\r
-// <i> F_cco0 = (2 * M * F_in) / N\r
-// <i> F_in must be in the range of 32 kHz to 50 MHz\r
-// <i> F_cco0 must be in the range of 275 MHz to 550 MHz\r
-// <o4.0..14> MSEL: PLL Multiplier Selection\r
-// <6-32768><#-1>\r
-// <i> M Value\r
-// <o4.16..23> NSEL: PLL Divider Selection\r
-// <1-256><#-1>\r
-// <i> N Value\r
-// </h>\r
-// </e>\r
-//\r
-// <e5> PLL1 Configuration (USB PLL)\r
-// <h> PLL1 Configuration Register (PLL1CFG)\r
-// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)\r
-// <i> F_cco1 = F_osc * M * 2 * P\r
-// <i> F_cco1 must be in the range of 156 MHz to 320 MHz\r
-// <o6.0..4> MSEL: PLL Multiplier Selection\r
-// <1-32><#-1>\r
-// <i> M Value (for USB maximum value is 4)\r
-// <o6.5..6> PSEL: PLL Divider Selection\r
-// <0=> 1\r
-// <1=> 2\r
-// <2=> 4\r
-// <3=> 8\r
-// <i> P Value\r
-// </h>\r
-// </e>\r
-//\r
-// <h> CPU Clock Configuration Register (CCLKCFG)\r
-// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0\r
-// <3-256><#-1>\r
-// </h>\r
-//\r
-// <h> USB Clock Configuration Register (USBCLKCFG)\r
-// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0\r
-// <0-15>\r
-// <i> Divide is USBSEL + 1\r
-// </h>\r
-//\r
-// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)\r
-// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 6\r
-// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 6\r
-// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 6\r
-// </h>\r
-//\r
-// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)\r
-// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM\r
-// <0=> Pclk = Cclk / 4\r
-// <1=> Pclk = Cclk\r
-// <2=> Pclk = Cclk / 2\r
-// <3=> Pclk = Hclk / 8\r
-// </h>\r
-//\r
-// <h> Power Control for Peripherals Register (PCONP)\r
-// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable\r
-// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable\r
-// <o11.3> PCUART0: UART 0 power/clock enable\r
-// <o11.4> PCUART1: UART 1 power/clock enable\r
-// <o11.6> PCPWM1: PWM 1 power/clock enable\r
-// <o11.7> PCI2C0: I2C interface 0 power/clock enable\r
-// <o11.8> PCSPI: SPI interface power/clock enable\r
-// <o11.9> PCRTC: RTC power/clock enable\r
-// <o11.10> PCSSP1: SSP interface 1 power/clock enable\r
-// <o11.12> PCAD: A/D converter power/clock enable\r
-// <o11.13> PCCAN1: CAN controller 1 power/clock enable\r
-// <o11.14> PCCAN2: CAN controller 2 power/clock enable\r
-// <o11.15> PCGPIO: GPIOs power/clock enable\r
-// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable\r
-// <o11.17> PCMC: Motor control PWM power/clock enable\r
-// <o11.18> PCQEI: Quadrature encoder interface power/clock enable\r
-// <o11.19> PCI2C1: I2C interface 1 power/clock enable\r
-// <o11.21> PCSSP0: SSP interface 0 power/clock enable\r
-// <o11.22> PCTIM2: Timer 2 power/clock enable\r
-// <o11.23> PCTIM3: Timer 3 power/clock enable\r
-// <o11.24> PCUART2: UART 2 power/clock enable\r
-// <o11.25> PCUART3: UART 3 power/clock enable\r
-// <o11.26> PCI2C2: I2C interface 2 power/clock enable\r
-// <o11.27> PCI2S: I2S interface power/clock enable\r
-// <o11.29> PCGPDMA: GP DMA function power/clock enable\r
-// <o11.30> PCENET: Ethernet block power/clock enable\r
-// <o11.31> PCUSB: USB interface power/clock enable\r
-// </h>\r
-//\r
-// <h> Clock Output Configuration Register (CLKOUTCFG)\r
-// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT\r
-// <0=> CPU clock\r
-// <1=> Main oscillator\r
-// <2=> Internal RC oscillator\r
-// <3=> USB clock\r
-// <4=> RTC oscillator\r
-// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT\r
-// <1-16><#-1>\r
-// <o12.8> CLKOUT_EN: CLKOUT enable control\r
-// </h>\r
-//\r
-// </e>\r
-*/\r
-#define CLOCK_SETUP 1\r
-#define SCS_Val 0x00000020\r
-#define CLKSRCSEL_Val 0x00000001\r
-#define PLL0_SETUP 1\r
-#define PLL0CFG_Val 0x00050063\r
-#define PLL1_SETUP 1\r
-#define PLL1CFG_Val 0x00000023\r
-#define CCLKCFG_Val 0x00000003\r
-#define USBCLKCFG_Val 0x00000000\r
-#define PCLKSEL0_Val 0x00000000\r
-#define PCLKSEL1_Val 0x00000000\r
-#define PCONP_Val 0x042887DE\r
-#define CLKOUTCFG_Val 0x00000000\r
-\r
-\r
-/*--------------------- Flash Accelerator Configuration ----------------------\r
-//\r
-// <e> Flash Accelerator Configuration\r
-// <o1.0..11> Reserved\r
-// <o1.12..15> FLASHTIM: Flash Access Time\r
-// <0=> 1 CPU clock (for CPU clock up to 20 MHz)\r
-// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)\r
-// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)\r
-// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)\r
-// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)\r
-// <5=> 6 CPU clocks (for any CPU clock)\r
-// </e>\r
-*/\r
-#define FLASH_SETUP 1\r
-#define FLASHCFG_Val 0x0000303A\r
-\r
-/*\r
-//-------- <<< end of configuration section >>> ------------------------------\r
-*/\r
-\r
-/*----------------------------------------------------------------------------\r
- Check the register settings\r
- *----------------------------------------------------------------------------*/\r
-#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))\r
-#define CHECK_RSVD(val, mask) (val & mask)\r
-\r
-/* Clock Configuration -------------------------------------------------------*/\r
-#if (CHECK_RSVD((SCS_Val), ~0x00000030))\r
- #error "SCS: Invalid values of reserved bits!"\r
-#endif\r
-\r
-#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))\r
- #error "CLKSRCSEL: Value out of range!"\r
-#endif\r
-\r
-#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))\r
- #error "PLL0CFG: Invalid values of reserved bits!"\r
-#endif\r
-\r
-#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))\r
- #error "PLL1CFG: Invalid values of reserved bits!"\r
-#endif\r
-\r
-#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))\r
- #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"\r
-#endif\r
-\r
-#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))\r
- #error "USBCLKCFG: Invalid values of reserved bits!"\r
-#endif\r
-\r
-#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))\r
- #error "PCLKSEL0: Invalid values of reserved bits!"\r
-#endif\r
-\r
-#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))\r
- #error "PCLKSEL1: Invalid values of reserved bits!"\r
-#endif\r
-\r
-#if (CHECK_RSVD((PCONP_Val), 0x10100821))\r
- #error "PCONP: Invalid values of reserved bits!"\r
-#endif\r
-\r
-#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))\r
- #error "CLKOUTCFG: Invalid values of reserved bits!"\r
-#endif\r
-\r
-/* Flash Accelerator Configuration -------------------------------------------*/\r
-#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))\r
- #error "FLASHCFG: Invalid values of reserved bits!"\r
-#endif\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- DEFINES\r
- *----------------------------------------------------------------------------*/\r
-\r
-/*----------------------------------------------------------------------------\r
- Define clocks\r
- *----------------------------------------------------------------------------*/\r
-#define XTAL (12000000UL) /* Oscillator frequency */\r
-#define OSC_CLK ( XTAL) /* Main oscillator frequency */\r
-#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */\r
-#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */\r
-\r
-\r
-/* F_cco0 = (2 * M * F_in) / N */\r
-#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)\r
-#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)\r
-#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)\r
-#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)\r
-\r
-/* Determine core clock frequency according to settings */\r
- #if (PLL0_SETUP)\r
- #if ((CLKSRCSEL_Val & 0x03) == 1)\r
- #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)\r
- #elif ((CLKSRCSEL_Val & 0x03) == 2)\r
- #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)\r
- #else\r
- #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)\r
- #endif\r
- #else\r
- #if ((CLKSRCSEL_Val & 0x03) == 1)\r
- #define __CORE_CLK (OSC_CLK / __CCLK_DIV)\r
- #elif ((CLKSRCSEL_Val & 0x03) == 2)\r
- #define __CORE_CLK (RTC_CLK / __CCLK_DIV)\r
- #else\r
- #define __CORE_CLK (IRC_OSC / __CCLK_DIV)\r
- #endif\r
- #endif\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Variable definitions\r
- *----------------------------------------------------------------------------*/\r
-uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock functions\r
- *----------------------------------------------------------------------------*/\r
-void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */\r
-{\r
- /* Determine clock frequency according to clock register values */\r
- if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */\r
- switch (LPC_SC->CLKSRCSEL & 0x03) {\r
- case 0: /* Int. RC oscillator => PLL0 */\r
- case 3: /* Reserved, default to Int. RC */\r
- SystemCoreClock = (IRC_OSC *\r
- ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /\r
- (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /\r
- ((LPC_SC->CCLKCFG & 0xFF)+ 1));\r
- break;\r
- case 1: /* Main oscillator => PLL0 */\r
- SystemCoreClock = (OSC_CLK *\r
- ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /\r
- (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /\r
- ((LPC_SC->CCLKCFG & 0xFF)+ 1));\r
- break;\r
- case 2: /* RTC oscillator => PLL0 */\r
- SystemCoreClock = (RTC_CLK *\r
- ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /\r
- (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /\r
- ((LPC_SC->CCLKCFG & 0xFF)+ 1));\r
- break;\r
- }\r
- } else {\r
- switch (LPC_SC->CLKSRCSEL & 0x03) {\r
- case 0: /* Int. RC oscillator => PLL0 */\r
- case 3: /* Reserved, default to Int. RC */\r
- SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);\r
- break;\r
- case 1: /* Main oscillator => PLL0 */\r
- SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);\r
- break;\r
- case 2: /* RTC oscillator => PLL0 */\r
- SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);\r
- break;\r
- }\r
- }\r
-\r
-}\r
-/* Exported types --------------------------------------------------------------*/\r
-/* Exported constants --------------------------------------------------------*/\r
-//extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */\r
-//extern unsigned long _sdata; /* start address for the .data section. defined in linker script */\r
-//extern unsigned long _edata; /* end address for the .data section. defined in linker script */\r
-//\r
-//extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */\r
-//extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */\r
-\r
-//void _init(void)\r
-//{\r
-// unsigned long *pulSrc, *pulDest;\r
-//\r
-// //\r
-// // Copy the data segment initializers from flash to SRAM in ROM mode\r
-// //\r
-//#if (__RAM_MODE__==0)\r
-// pulSrc = &_sidata;\r
-// for(pulDest = &_sdata; pulDest < &_edata; )\r
-// {\r
-// *(pulDest++) = *(pulSrc++);\r
-// }\r
-//#endif\r
-//\r
-//\r
-// //\r
-// // Zero fill the bss segment.\r
-// //\r
-// for(pulDest = &_sbss; pulDest < &_ebss; )\r
-// {\r
-// *(pulDest++) = 0;\r
-// }\r
-//}\r
-\r
-/**\r
- * Initialize the system\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * @brief Setup the microcontroller system.\r
- * Initialize the System.\r
- */\r
-void SystemInit (void)\r
-{\r
-\r
-#if (CLOCK_SETUP) /* Clock Setup */\r
- LPC_SC->SCS = SCS_Val;\r
- if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */\r
- while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */\r
- }\r
-\r
- LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */\r
- LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */\r
- LPC_SC->PCLKSEL1 = PCLKSEL1_Val;\r
-\r
-#if (PLL0_SETUP)\r
- LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */\r
-\r
- LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */\r
- LPC_SC->PLL0FEED = 0xAA;\r
- LPC_SC->PLL0FEED = 0x55;\r
-\r
- LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */\r
- LPC_SC->PLL0FEED = 0xAA;\r
- LPC_SC->PLL0FEED = 0x55;\r
- while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */\r
-\r
- LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */\r
- LPC_SC->PLL0FEED = 0xAA;\r
- LPC_SC->PLL0FEED = 0x55;\r
- while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */\r
-#endif\r
-\r
-#if (PLL1_SETUP)\r
- LPC_SC->PLL1CFG = PLL1CFG_Val;\r
- LPC_SC->PLL1FEED = 0xAA;\r
- LPC_SC->PLL1FEED = 0x55;\r
-\r
- LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */\r
- LPC_SC->PLL1FEED = 0xAA;\r
- LPC_SC->PLL1FEED = 0x55;\r
- while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */\r
-\r
- LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */\r
- LPC_SC->PLL1FEED = 0xAA;\r
- LPC_SC->PLL1FEED = 0x55;\r
- while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */\r
-#else\r
- LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */\r
-#endif\r
- LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */\r
-\r
- LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */\r
-#endif\r
-\r
-#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */\r
- LPC_SC->FLASHCFG = FLASHCFG_Val;\r
-#endif\r
-}\r
+++ /dev/null
-system_LPC17xx.o: CMSIS/system_LPC17xx.c CMSIS/LPC17xx.h CMSIS/core_cm3.h \\r
- CMSIS/system_LPC17xx.h\r
-\r
-CMSIS/LPC17xx.h:\r
-\r
-CMSIS/core_cm3.h:\r
-\r
-CMSIS/system_LPC17xx.h:\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file system_LPC17xx.h\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File\r
- * for the NXP LPC17xx Device Series\r
- * @version V1.02\r
- * @date 08. September 2009\r
- *\r
- * @note\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
- * processor based microcontrollers. This file can be freely distributed\r
- * within development tools that are supporting such ARM based processors.\r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-\r
-#ifndef __SYSTEM_LPC17xx_H\r
-#define __SYSTEM_LPC17xx_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-#include <stdint.h>\r
-\r
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
-\r
-\r
-/**\r
- * Initialize the system\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * @brief Setup the microcontroller system.\r
- * Initialize the System and update the SystemCoreClock variable.\r
- */\r
-extern void SystemInit (void);\r
-\r
-/**\r
- * Update SystemCoreClock variable\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * @brief Updates the SystemCoreClock with current core Clock\r
- * retrieved from cpu registers.\r
- */\r
-extern void SystemCoreClockUpdate (void);\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __SYSTEM_LPC17xx_H */\r
+++ /dev/null
-/*
- * This is the NXP LPC1768 linker file for code running from flash.
- *
- * TODO:
- * - handle the exotic input sections (e.g. glue and veneer, C++ sections)
- * - add additional Ethernet and USB RAM memory regions (2x16k)
- * - add boot ROM memory regions
- *
- * See also: http://bitbucket.org/jpc/lpc1768/
- *
- * Copyright (c) 2010 LoEE - Jakub Piotr Cłapa
- * This program is released under the new BSD license.
- */
-OUTPUT_FORMAT("elf32-littlearm")
-OUTPUT_ARCH(arm)
-
-ENTRY(Reset_Handler)
-
-MEMORY {
- flash (rx) : ORIGIN = 0x00000000, LENGTH = 512K
- ram (rwx) : ORIGIN = 0x10000000, LENGTH = 32K
-}
-
-SECTIONS {
- . = 0;
-
- .text : {
- _stext = .;
- KEEP(*(.cs3.interrupt_vector))
- *(.text*)
- *(.rodata*)
- . = ALIGN(4);
- _etext = .;
- } > flash
-
- .data : {
- _sdata = .;
- *(.data*)
- _edata = .;
- } > ram AT > flash
-
- .bss : {
- _sbss = .;
- *(.bss*)
- . = ALIGN(4);
- _ebss = .;
- } > ram
-
- _sstack = ORIGIN(ram) + LENGTH(ram);
-}
+++ /dev/null
-# Copyright (c) 2008-2010 Jakub Piotr Cłapa
-# This program is released under the new BSD license.
-ARCH = /home/asbjorn/dev/armchain/arm-none-eabi/bin/arm-none-eabi
-MBED_VOLUME = /Volumes/MBED
-
-# Tool definitions
-CC = $(ARCH)-gcc
-LD = $(ARCH)-ld
-AR = $(ARCH)-ar
-AS = $(ARCH)-as
-CP = $(ARCH)-objcopy
-OD = $(ARCH)-objdump
-SIZE = $(ARCH)-size
-RM = rm
-Q = @./quiet "$@"
-
-# Flags
-CFLAGS = -W -Wall -Os --std=gnu99 -fgnu89-inline -mcpu=cortex-m3 -mthumb
-CFLAGS += -ffunction-sections -fdata-sections
-ASFLAGS =
-LDFLAGS = --gc-sections
-CPFLAGS =
-ODFLAGS = -x --syms
-PRFLAGS ?=
-
-# Source files
-LINKER_SCRIPT = LPC1768-flash.ld
-CSRCS = startup.c $(wildcard CMSIS/*.c)
-CSRCS += main.c
-ASRCS =
-
-
-OBJS = $(CSRCS:.c=.o) $(ASRCS:.s=.o)
-
-.PHONY: all size clean nuke
-
-all: main.bin main.hex
-
-isp: main.bin
- @./quiet $< cp $^ $(MBED_VOLUME)/
-
-size: main.elf
- @$(SIZE) $<
-
-%.hex: %.elf
- $Q $(CP) $(CPFLAGS) -O ihex $< $*.hex
-
-%.bin: %.elf
- $Q $(CP) $(CPFLAGS) -O binary $< $*.bin
-
-main.elf: $(LINKER_SCRIPT) $(OBJS)
- $Q $(LD) -Map $(@:.elf=.map) $(LDFLAGS) -T $^ -o $@
- $Q $(OD) $(ODFLAGS) $@ > $(@:.elf=.dump)
- @$(SIZE) $@
-
-%.o: %.c
- @$(CC) -MM $< -MF $*.d -MP
- $Q $(CC) -c $(CFLAGS) $< -o $@
-
-%.o: %.S
- $Q $(AS) $(ASFLAGS) $< -o $@
-
-io-pin.h: io-pin.ss
- $Q mzscheme $< > $@
-
-clean:
- @-rm -f *.elf quiet.log
- @-\
-for D in "." "**"; do \
- rm -f $$D/*.o $$D/*.d $$D/*.lst $$D/*.dump $$D/*.map; \
-done
-
-nuke: clean
- -rm -f *.hex *.bin
-
--include $(CSRCS:.c=.d)
+++ /dev/null
-/*
- * IO functions for NXP LPC1768. (generated file, check io-pin.ss)
- *
- * See also: http://bitbucket.org/jpc/lpc1768/
- *
- * Copyright (c) 2010 LoEE - Jakub Piotr Cłapa
- * This program is released under the new BSD license.
- */
-#ifndef IO_PIN_H
-#define IO_PIN_H
-
-#include "CMSIS/LPC17xx.h"
-
-enum pin_port {
-P0 = 0,
-P1 = 32,
-P2 = 64,
-P3 = 96,
-P4 = 128,
-};
-
-enum pin_dir {
- PIN_IN = 0,
- PIN_OUT = 1,
-};
-
-extern void invalid_pin_error () __attribute__((error ("Invalid IO pin number.")));
-
-extern __inline__ __attribute__((always_inline))
-int pin_read (int pin_no)
-{
- switch(pin_no) {
- case 0 ... 31:
- return LPC_GPIO0->FIOPIN & (1 << (pin_no - 0));
- case 32 ... 63:
- return LPC_GPIO1->FIOPIN & (1 << (pin_no - 32));
- case 64 ... 95:
- return LPC_GPIO2->FIOPIN & (1 << (pin_no - 64));
- case 96 ... 127:
- return LPC_GPIO3->FIOPIN & (1 << (pin_no - 96));
- case 128 ... 159:
- return LPC_GPIO4->FIOPIN & (1 << (pin_no - 128));
- default:
- invalid_pin_error ();
- break;
- }
- return 0;
-}
-
-extern __inline__ __attribute__((always_inline))
-void pin_write (int pin_no, int value)
-{
- switch(pin_no) {
- case 0 ... 31:
- if (value) {
- LPC_GPIO0->FIOSET = (1 << (pin_no - 0));
- } else {
- LPC_GPIO0->FIOCLR = (1 << (pin_no - 0));
- }
- break;
- case 32 ... 63:
- if (value) {
- LPC_GPIO1->FIOSET = (1 << (pin_no - 32));
- } else {
- LPC_GPIO1->FIOCLR = (1 << (pin_no - 32));
- }
- break;
- case 64 ... 95:
- if (value) {
- LPC_GPIO2->FIOSET = (1 << (pin_no - 64));
- } else {
- LPC_GPIO2->FIOCLR = (1 << (pin_no - 64));
- }
- break;
- case 96 ... 127:
- if (value) {
- LPC_GPIO3->FIOSET = (1 << (pin_no - 96));
- } else {
- LPC_GPIO3->FIOCLR = (1 << (pin_no - 96));
- }
- break;
- case 128 ... 159:
- if (value) {
- LPC_GPIO4->FIOSET = (1 << (pin_no - 128));
- } else {
- LPC_GPIO4->FIOCLR = (1 << (pin_no - 128));
- }
- break;
- default:
- invalid_pin_error ();
- break;
- }
-}
-
-extern __inline__ __attribute__((always_inline))
-void pin_dir (int pin_no, enum pin_dir dir)
-{
- switch(pin_no) {
- case 0 ... 31:
- if (dir == PIN_OUT) {
- LPC_GPIO0->FIODIR |= (1 << (pin_no - 0));
- } else {
- LPC_GPIO0->FIODIR &= (1 << (pin_no - 0));
- }
- break;
- case 32 ... 63:
- if (dir == PIN_OUT) {
- LPC_GPIO1->FIODIR |= (1 << (pin_no - 32));
- } else {
- LPC_GPIO1->FIODIR &= (1 << (pin_no - 32));
- }
- break;
- case 64 ... 95:
- if (dir == PIN_OUT) {
- LPC_GPIO2->FIODIR |= (1 << (pin_no - 64));
- } else {
- LPC_GPIO2->FIODIR &= (1 << (pin_no - 64));
- }
- break;
- case 96 ... 127:
- if (dir == PIN_OUT) {
- LPC_GPIO3->FIODIR |= (1 << (pin_no - 96));
- } else {
- LPC_GPIO3->FIODIR &= (1 << (pin_no - 96));
- }
- break;
- case 128 ... 159:
- if (dir == PIN_OUT) {
- LPC_GPIO4->FIODIR |= (1 << (pin_no - 128));
- } else {
- LPC_GPIO4->FIODIR &= (1 << (pin_no - 128));
- }
- break;
- default:
- invalid_pin_error ();
- break;
- }
-}
-
-#endif
\ No newline at end of file
+++ /dev/null
-#lang scribble/text
-@(define ports '(P0 P1 P2 P3 P4))
-@(define registers '(LPC_GPIO0 LPC_GPIO1 LPC_GPIO2 LPC_GPIO3 LPC_GPIO4))
-/*
- * IO functions for NXP LPC1768. (generated file, check io-pin.ss)
- *
- * See also: http://bitbucket.org/jpc/lpc1768/
- *
- * Copyright (c) 2010 LoEE - Jakub Piotr Cłapa
- * This program is released under the new BSD license.
- */
-#ifndef IO_PIN_H
-#define IO_PIN_H
-
-#include "CMSIS/LPC17xx.h"
-
-enum pin_port {
-@(add-newlines
- (for/list ([i (in-naturals)]
- [port ports])
- @list{@port = @(* i 32),}))
-};
-
-enum pin_dir {
- PIN_IN = 0,
- PIN_OUT = 1,
-};
-
-extern void invalid_pin_error () __attribute__((error ("Invalid IO pin number.")));
-
-@(define INLINE "extern __inline__ __attribute__((always_inline))")
-@(define-syntax-rule (switch pin_no i register template)
- @list{switch(pin_no) {
- @(add-newlines
- (for/list ([i (in-naturals)]
- [register registers])
- @list{case @(* i 32) ... @(sub1 (* (add1 i) 32)):
- @template}))
- default:
- invalid_pin_error ();
- break;
- }})
-
-@INLINE
-int pin_read (int pin_no)
-{
- @(switch @{pin_no} i register
- @list{return @|register|->FIOPIN & (1 << (pin_no - @(* i 32)));})
- return 0;
-}
-
-@INLINE
-void pin_write (int pin_no, int value)
-{
- @(switch @{pin_no} i register
- @list{if (value) {
- @|register|->FIOSET = (1 << (pin_no - @(* i 32)));
- } else {
- @|register|->FIOCLR = (1 << (pin_no - @(* i 32)));
- }
- break;})
-}
-
-@INLINE
-void pin_dir (int pin_no, enum pin_dir dir)
-{
- @(switch @{pin_no} i register
- @list{if (dir == PIN_OUT) {
- @|register|->FIODIR @"|=" (1 << (pin_no - @(* i 32)));
- } else {
- @|register|->FIODIR @"&=" (1 << (pin_no - @(* i 32)));
- }
- break;})
-}
-
-#endif
\ No newline at end of file
+++ /dev/null
-CC = gcc\r
-LD = gcc\r
-LDFLAGS = -Wall -O4 -std=c99\r
-EXES = lpcrc\r
-\r
-all: $(EXES)\r
-\r
-% : %.c\r
- $(LD) $(LDFLAGS) -o $@ $<\r
-\r
-clean: \r
- rm -f $(EXES)\r
+++ /dev/null
-/*\r
- * Software License Agreement (BSD License)\r
- *\r
- * Copyright (c) 2010, Roel Verdult\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are met:\r
- * 1. Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * 2. Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- * 3. Neither the name of the copyright holders nor the\r
- * names of its contributors may be used to endorse or promote products\r
- * derived from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY\r
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY\r
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\r
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- */\r
-\r
-#include <stdio.h>\r
-#include <stdint.h>\r
-\r
-#define BLOCK_COUNT 7\r
-#define BLOCK_LENGTH 4\r
-#define BLOCK_TOTAL (BLOCK_COUNT*BLOCK_LENGTH)\r
-\r
-typedef unsigned char byte_t;\r
-\r
-int main(int argc, char *argv[])\r
-{\r
- FILE* pf;\r
- byte_t buf[BLOCK_TOTAL];\r
- uint32_t crc = 0;\r
- uint32_t block;\r
- \r
- // Check for required arguments\r
- if (argc < 2)\r
- {\r
- printf("syntax: lpcrc <firmware.bin>\n");\r
- return 1;\r
- }\r
- \r
- // Try to open the supplied firmware\r
- if ((pf = fopen(argv[1],"rb+")) == NULL)\r
- {\r
- printf("error: could not open file [%s] with write access\n",argv[1]);\r
- return 1;\r
- }\r
-\r
- // Read out the data blocks used for crc calculation\r
- if (fread(buf,1,BLOCK_TOTAL,pf) != BLOCK_TOTAL)\r
- {\r
- printf("error: could not read required bytes\n");\r
- fclose(pf);\r
- return 1;\r
- }\r
-\r
- // Compute the crc value\r
- for (block=0; block<BLOCK_COUNT; block++)\r
- {\r
- crc += *((uint32_t*)(buf+(block*BLOCK_LENGTH)));\r
- }\r
- crc = (~crc) + 1;\r
- \r
- // Reposition the file stream indicator to switch between read and write\r
- if (fseek(pf,0,SEEK_CUR) != 0)\r
- {\r
- printf("error: could not switch from read to write mode\n");\r
- fclose(pf);\r
- return 1;\r
- }\r
- \r
- // Write the crc back to the file\r
- if (fwrite((byte_t*)&crc,1,BLOCK_LENGTH,pf) != BLOCK_LENGTH)\r
- {\r
- printf("error: could not write crc back to file\n");\r
- fclose(pf);\r
- return 1;\r
- }\r
-\r
- printf("succesfully updated crc to: %08x\n",crc);\r
- fclose(pf);\r
- \r
- return 0;\r
-}\r
-\r
+++ /dev/null
-/*
- * LED blinking example for the mbed LPC1768-based board.
- *
- * See also: http://bitbucket.org/jpc/lpc1768/
- *
- * Copyright (c) 2010 LoEE - Jakub Piotr Cłapa
- * This program is released under the new BSD license.
- */
-#include "CMSIS/LPC17xx.h"
-#include "io-pin.h"
-
-// For mbed-005.1
-#define LED1 P1+18
-#define LED2 P1+20
-#define LED3 P1+21
-#define LED4 P1+29
-
-// Helper macros
-#define LED_ON(i) (pin_write (LED##i, 1))
-#define LED_OFF(i) (pin_write (LED##i, 0))
-
-volatile uint32_t current_time;
-
-void SysTick_Handler (void)
-{
- current_time++;
-}
-
-void delay (uint32_t interval)
-{
- uint32_t start = current_time;
- while (current_time - start < interval);
-}
-
-int main (void)
-{
- // Setup SysTick interrupts at 1kHz (1ms)
- SysTick_Config (SystemCoreClock / 1000);
-
- // Configure as output pins.
- pin_dir (LED1, PIN_OUT);
- pin_dir (LED2, PIN_OUT);
- pin_dir (LED3, PIN_OUT);
- pin_dir (LED4, PIN_OUT);
-
- // Twinkle!
- while(1) {
- LED_OFF(1); delay (120); LED_ON(1);
- LED_ON(2); delay (120); LED_OFF(2);
- LED_ON(3); delay (120); LED_OFF(3);
- LED_ON(4); delay (120); LED_OFF(4);
- LED_ON(3); delay (120); LED_OFF(3);
- LED_ON(2); delay (120); LED_OFF(2);
- }
-}
+++ /dev/null
-main.o: main.c CMSIS/LPC17xx.h CMSIS/core_cm3.h CMSIS/system_LPC17xx.h \\r
- io-pin.h\r
-\r
-CMSIS/LPC17xx.h:\r
-\r
-CMSIS/core_cm3.h:\r
-\r
-CMSIS/system_LPC17xx.h:\r
-\r
-io-pin.h:\r
+++ /dev/null
-\r
-main.elf: file format elf32-littlearm\r
-main.elf\r
-architecture: arm, flags 0x00000112:\r
-EXEC_P, HAS_SYMS, D_PAGED\r
-start address 0x00000041\r
-\r
-Program Header:\r
- LOAD off 0x00008000 vaddr 0x00000000 paddr 0x00000000 align 2**15\r
- filesz 0x00000234 memsz 0x00000234 flags r-x\r
- LOAD off 0x00010000 vaddr 0x10000000 paddr 0x00000234 align 2**15\r
- filesz 0x00000004 memsz 0x00000008 flags rw-\r
-private flags = 5000002: [Version5 EABI] [has entry point]\r
-\r
-Sections:\r
-Idx Name Size VMA LMA File off Algn\r
- 0 .text 00000234 00000000 00000000 00008000 2**2\r
- CONTENTS, ALLOC, LOAD, READONLY, CODE\r
- 1 .data 00000004 10000000 00000234 00010000 2**2\r
- CONTENTS, ALLOC, LOAD, DATA\r
- 2 .bss 00000004 10000004 00000238 00010004 2**2\r
- ALLOC\r
- 3 .comment 00000011 00000000 00000000 00010004 2**0\r
- CONTENTS, READONLY\r
- 4 .ARM.attributes 00000031 00000000 00000000 00010015 2**0\r
- CONTENTS, READONLY\r
-SYMBOL TABLE:\r
-00000000 l d .text 00000000 .text\r
-10000000 l d .data 00000000 .data\r
-10000004 l d .bss 00000000 .bss\r
-00000000 l d .comment 00000000 .comment\r
-00000000 l d .ARM.attributes 00000000 .ARM.attributes\r
-00000000 l df *ABS* 00000000 startup.c\r
-00000000 l df *ABS* 00000000 system_LPC17xx.c\r
-00000000 l df *ABS* 00000000 main.c\r
-00000168 l F .text 00000014 delay.clone.0\r
-00000084 w F .text 00000002 DebugMon_Handler\r
-00000084 w F .text 00000002 HardFault_Handler\r
-0000017c g F .text 00000010 SysTick_Handler\r
-00000084 w F .text 00000002 PendSV_Handler\r
-00000084 w F .text 00000002 NMI_Handler\r
-00000234 g .text 00000000 _etext\r
-10000004 g .bss 00000000 _sbss\r
-10000004 g O .bss 00000004 current_time\r
-10000000 g O .data 00000004 SystemCoreClock\r
-00000084 w F .text 00000002 UsageFault_Handler\r
-10000000 g .data 00000000 _sdata\r
-10000004 g .bss 00000000 _ebss\r
-00000040 w F .text 00000044 Reset_Handler\r
-00000084 g F .text 00000002 Default_Handler\r
-00000000 g O .text 00000040 interrupt_vectors\r
-00000084 w F .text 00000002 MemManage_Handler\r
-0000018c g F .text 000000a8 main\r
-00000084 w F .text 00000002 SVC_Handler\r
-00000088 g F .text 000000e0 SystemInit\r
-10008000 g *ABS* 00000000 _sstack\r
-10000004 g .data 00000000 _edata\r
-00000084 w F .text 00000002 BusFault_Handler\r
-00000000 g .text 00000000 _stext\r
-\r
-\r
+++ /dev/null
-:100000000080001041000000850000008500000015\r
-:10001000850000008500000085000000267DFFEFC0\r
-:10002000000000000000000000000000850000004B\r
-:100030008500000000000000850000007D01000038\r
-:1000400008B500F021F80A4A0A4B0B4903E052F8C0\r
-:10005000040B43F8040B8B42F9D3084B08490022E8\r
-:1000600001E043F8042B8B42FBD300F08FF8FEE74E\r
-:100070003402000000000010040000100400001012\r
-:1000800004000010FEE70000344B2022C3F8A0213A\r
-:100090001A46D2F8A011314B11F0400FF9D00322CB\r
-:1000A000C3F804210022C3F8A821C3F8AC212C4ACC\r
-:1000B0000120C3F80C01AA21C3F884205522C3F8FB\r
-:1000C0008C10C3F88C20C3F88000C3F88C10C3F8E0\r
-:1000D0008C20D3F88810214A11F0806FF9D00323C7\r
-:1000E000C2F88030A733C2F88C305523C2F88C3068\r
-:1000F000D2F88810194B11F0407FF9D02322C3F8B1\r
-:10010000A420AA2132320120C3F8AC10C3F8AC20DD\r
-:10011000C3F8A000C3F8AC10C3F8AC20D3F8A81003\r
-:100120000E4A11F4806FF9D00323C2F8A030A73330\r
-:10013000C2F8AC305523C2F8AC30D2F8A810074B47\r
-:1001400011F4407FF9D0074AC3F8C4200022C3F855\r
-:10015000C82143F23A021A60704700BF00C00F4046\r
-:1001600063000500DE872804034B1A681968891AA2\r
-:100170007729FBD9704700BF04000010024B1A68B2\r
-:1001800001321A60704700BF04000010254BF7B51C\r
-:100190001A684FF47A73B2FBF3F222F07F42224BDB\r
-:1001A000013A5A60214AF82182F8231000229A600D\r
-:1001B0001F4C07321A6023684FF4802743F48023D2\r
-:1001C000236023683A4643F48013236023684FF486\r
-:1001D000801643F40013236023684FF4001543F0A6\r
-:1001E00000532360E2610092FFF7BEFFA761A661A2\r
-:1001F000FFF7BAFFE661A561FFF7B6FF4FF00053C6\r
-:10020000E561A3610193FFF7AFFF019BE361A56186\r
-:10021000FFF7AAFFE561A661FFF7A6FFE661009A76\r
-:10022000E0E700BF0000001010E000E000ED00E09B\r
-:0402300020C00920C1\r
-:0402340000E1F505EB\r
-:0400000300000041B8\r
-:00000001FF\r
+++ /dev/null
-\r
-Allocating common symbols\r
-Common symbol size file\r
-\r
-current_time 0x4 main.o\r
-\r
-Discarded input sections\r
-\r
- .text 0x0000000000000000 0x0 startup.o\r
- .data 0x0000000000000000 0x0 startup.o\r
- .bss 0x0000000000000000 0x0 startup.o\r
- .text 0x0000000000000000 0x0 CMSIS/system_LPC17xx.o\r
- .data 0x0000000000000000 0x0 CMSIS/system_LPC17xx.o\r
- .bss 0x0000000000000000 0x0 CMSIS/system_LPC17xx.o\r
- .text.SystemCoreClockUpdate\r
- 0x0000000000000000 0xfc CMSIS/system_LPC17xx.o\r
- .text 0x0000000000000000 0x0 main.o\r
- .data 0x0000000000000000 0x0 main.o\r
- .bss 0x0000000000000000 0x0 main.o\r
- .text.delay 0x0000000000000000 0x14 main.o\r
-\r
-Memory Configuration\r
-\r
-Name Origin Length Attributes\r
-flash 0x0000000000000000 0x0000000000080000 xr\r
-ram 0x0000000010000000 0x0000000000008000 xrw\r
-*default* 0x0000000000000000 0xffffffffffffffff\r
-\r
-Linker script and memory map\r
-\r
- 0x0000000000000000 . = 0x0\r
-\r
-.text 0x0000000000000000 0x234\r
- 0x0000000000000000 _stext = .\r
- *(.cs3.interrupt_vector)\r
- .cs3.interrupt_vector\r
- 0x0000000000000000 0x40 startup.o\r
- 0x0000000000000000 interrupt_vectors\r
- *(.text*)\r
- .text.Reset_Handler\r
- 0x0000000000000040 0x44 startup.o\r
- 0x0000000000000040 Reset_Handler\r
- .text.Default_Handler\r
- 0x0000000000000084 0x2 startup.o\r
- 0x0000000000000084 DebugMon_Handler\r
- 0x0000000000000084 HardFault_Handler\r
- 0x0000000000000084 PendSV_Handler\r
- 0x0000000000000084 NMI_Handler\r
- 0x0000000000000084 UsageFault_Handler\r
- 0x0000000000000084 Default_Handler\r
- 0x0000000000000084 MemManage_Handler\r
- 0x0000000000000084 SVC_Handler\r
- 0x0000000000000084 BusFault_Handler\r
- *fill* 0x0000000000000086 0x2 00\r
- .text.SystemInit\r
- 0x0000000000000088 0xe0 CMSIS/system_LPC17xx.o\r
- 0x0000000000000088 SystemInit\r
- .text.delay.clone.0\r
- 0x0000000000000168 0x14 main.o\r
- .text.SysTick_Handler\r
- 0x000000000000017c 0x10 main.o\r
- 0x000000000000017c SysTick_Handler\r
- .text.main 0x000000000000018c 0xa8 main.o\r
- 0x000000000000018c main\r
- *(.rodata*)\r
- 0x0000000000000234 . = ALIGN (0x4)\r
- 0x0000000000000234 _etext = .\r
-\r
-.glue_7 0x0000000000000234 0x0\r
- .glue_7 0x0000000000000000 0x0 linker stubs\r
-\r
-.glue_7t 0x0000000000000234 0x0\r
- .glue_7t 0x0000000000000000 0x0 linker stubs\r
-\r
-.vfp11_veneer 0x0000000000000234 0x0\r
- .vfp11_veneer 0x0000000000000000 0x0 linker stubs\r
-\r
-.v4_bx 0x0000000000000234 0x0\r
- .v4_bx 0x0000000000000000 0x0 linker stubs\r
-\r
-.data 0x0000000010000000 0x4 load address 0x0000000000000234\r
- 0x0000000010000000 _sdata = .\r
- *(.data*)\r
- .data.SystemCoreClock\r
- 0x0000000010000000 0x4 CMSIS/system_LPC17xx.o\r
- 0x0000000010000000 SystemCoreClock\r
- 0x0000000010000004 _edata = .\r
-\r
-.bss 0x0000000010000004 0x4 load address 0x0000000000000238\r
- 0x0000000010000004 _sbss = .\r
- *(.bss*)\r
- 0x0000000010000004 . = ALIGN (0x4)\r
- 0x0000000010000004 _ebss = .\r
- COMMON 0x0000000010000004 0x4 main.o\r
- 0x0000000010000004 current_time\r
- 0x0000000010008000 _sstack = 0x10008000\r
-LOAD startup.o\r
-LOAD CMSIS/system_LPC17xx.o\r
-LOAD main.o\r
-OUTPUT(main.elf elf32-littlearm)\r
-\r
-.comment 0x0000000000000000 0x11\r
- .comment 0x0000000000000000 0x11 startup.o\r
- 0x12 (size before relaxing)\r
- .comment 0x0000000000000000 0x12 CMSIS/system_LPC17xx.o\r
- .comment 0x0000000000000000 0x12 main.o\r
-\r
-.ARM.attributes\r
- 0x0000000000000000 0x31\r
- .ARM.attributes\r
- 0x0000000000000000 0x31 startup.o\r
- .ARM.attributes\r
- 0x0000000000000031 0x31 CMSIS/system_LPC17xx.o\r
- .ARM.attributes\r
- 0x0000000000000062 0x31 main.o\r
+++ /dev/null
-# The IMX31PDK eval board has a single IMX31 chip\r
-source [find interface/ngxtech.cfg]\r
-source [find target/lpc1768.cfg]\r
+++ /dev/null
-#!/bin/sh\r
-HELP='Usage:\r
- quiet fname cmd args ...\r
-\r
-Runs the passed in command printing only "cmd" and "fname" unless an\r
-error occurs in which case it prints the whole command line and\r
-colorized program output. Useful for running compilation commands since\r
-it removes the cluter, making it easier to spot errors and warnings.\r
-\r
-'\r
-# Copyright (c) 2008-2010 LoEE\r
-# This program is released under the new BSD license.\r
-\r
-if [ $# -lt 2 ]; then\r
- printf "$HELP"\r
- exit\r
-fi\r
-\r
-GREEN=""\r
-RED=""\r
-NORM=""\r
-if [ "$TERM@" = "rxvt@" ]; then\r
- GREEN="printf \033[32m"\r
- RED="printf \033[31m"\r
- YELLOW="printf \033[33m" # this is not yellow :)\r
- NORM="printf \033[m\017"\r
-fi\r
-if [ "$OSTYPE@" = "msys@" ]; then\r
- OLDATTR=$(eecolor.exe)\r
- GREEN="eecolor.exe 0 10"\r
- RED="eecolor.exe 0 12" \r
- YELLOW="eecolor 0 14"\r
- NORM="eecolor.exe ${OLDATTR}" \r
-fi\r
-\r
-MSG="$(printf "%-16s $1" "$2")"\r
-shift;\r
-\r
-printf "${MSG}\r" 1>&2\r
-\r
-rm -f quiet.log\r
-"$@" 2>> quiet.log\r
-RET=$?\r
-# if we check $? we won't notice the warnings\r
-if [ $RET -ne 0 -o -s quiet.log ]; then\r
- echo "$@" >& 2\r
- if [ $RET -ne 0 ]; then\r
- $RED >& 2\r
- else \r
- $YELLOW >& 2\r
- fi\r
- cat quiet.log >& 2\r
- $NORM &> 2\r
-\r
- exit $RET\r
-else\r
- $GREEN >& 2\r
- printf "${MSG}\n" 1>&2\r
- $NORM >& 2\r
-fi\r
-rm quiet.log\r
-exit $RET\r
+++ /dev/null
-/*
- * This is an ARM Cortex-M3 startup file for the NXP LPC1768.
- *
- * TODO: Add vendor (NXP) specific interrupt vectors.
- *
- * See also: http://bitbucket.org/jpc/lpc1768/
- *
- * Copyright (c) 2010 LoEE - Jakub Piotr Cłapa
- * This program is released under the new BSD license.
- */
-#include "CMSIS/LPC17xx.h"
-
-// Dummy handler.
-void Default_Handler (void) { while (1); }
-
-// Weakly bind all interrupt vectors to the dummy handler.
-void __attribute__((weak)) Reset_Handler(void);
-void __attribute__((weak)) NMI_Handler(void);
-void __attribute__((weak)) HardFault_Handler(void);
-void __attribute__((weak)) MemManage_Handler(void);
-void __attribute__((weak)) BusFault_Handler(void);
-void __attribute__((weak)) UsageFault_Handler(void);
-void __attribute__((weak)) SVC_Handler(void);
-void __attribute__((weak)) DebugMon_Handler(void);
-void __attribute__((weak)) PendSV_Handler(void);
-void __attribute__((weak)) SysTick_Handler(void);
-#pragma weak NMI_Handler = Default_Handler
-#pragma weak HardFault_Handler = Default_Handler
-#pragma weak MemManage_Handler = Default_Handler
-#pragma weak BusFault_Handler = Default_Handler
-#pragma weak UsageFault_Handler = Default_Handler
-#pragma weak SVC_Handler = Default_Handler
-#pragma weak DebugMon_Handler = Default_Handler
-#pragma weak PendSV_Handler = Default_Handler
-#pragma weak SysTick_Handler = Default_Handler
-
-// Start of the stack (last RAM address; exported in the linker script)
-extern void _sstack;
-
-// The signature of Cortex-M3 interrupt handlers.
-typedef void (* const Interrupt_Handler_P)(void);
-
-// Interrupt vectors table
-__attribute__ ((section(".cs3.interrupt_vector")))
-Interrupt_Handler_P interrupt_vectors[] = {
- &_sstack, // the first word contains the initial
- // stack pointer the hardware loads it
- // to the SP register before the first
- // instruction
- // Standard Cortex-M3 interrupts:
- Reset_Handler,
- NMI_Handler,
- HardFault_Handler,
- MemManage_Handler,
- BusFault_Handler,
- UsageFault_Handler,
- 0xefff7d26,
- 0,
- 0,
- 0,
- SVC_Handler,
- DebugMon_Handler,
- 0,
- PendSV_Handler,
- SysTick_Handler,
- // Vendor specific interrupts for LPC1768:
-};
-
-extern int main (void);
-
-extern uint32_t _etext, _sdata, _edata, _sbss, _ebss;
-
-void
-Reset_Handler(void)
-{
- // Initialize clocks
- SystemInit ();
-
- uint32_t *s, *d;
- // Copy initialization data to RAM (.data section)
- s = &_etext;
- d = &_sdata;
- while (d < &_edata) *d++ = *s++;
- // Zero the remaining allocated RAM (.bss section)
- d = &_sbss;
- while (d < &_ebss) *d++ = 0;
-
- // Everything is ready. Run the user program.
- main();
- while (1);
-}
+++ /dev/null
-startup.o: startup.c CMSIS/LPC17xx.h CMSIS/core_cm3.h \\r
- CMSIS/system_LPC17xx.h\r
-\r
-CMSIS/LPC17xx.h:\r
-\r
-CMSIS/core_cm3.h:\r
-\r
-CMSIS/system_LPC17xx.h:\r
git.asbjorn.biz / rapper.git / commitdiff